In present semiconductor technology, CMOS devices, such as n-FETs and p-FETs, are typically fabricated upon semiconductor wafers that each has a substrate surface oriented along one of a single set of equivalent crystal planes of the semiconductor material (e.g., Si) that forms the substrate. In particular, most of todays semiconductor devices are built upon silicon wafers having wafer surfaces oriented along one of the {100} crystal planes of silicon.
Electrons are known to have a high mobility along the {100} crystal planes of silicon, but holes are known to have high mobility along the {110} crystal planes of silicon. Specifically, hole mobility values along the {100} planes are roughly about 2 to 4 times lower than the corresponding electron mobility values along such planes. In contrast, hole mobility values along the {110} silicon surfaces are about 2 times higher than those along the {100} silicon surfaces, but electron mobility along the {110} surfaces are significantly degraded compared to those along the {100} surfaces.
As can be deduced from the above, the {110} silicon surfaces are optimal for forming p-FET devices due to the excellent hole mobility along the {110} planes, which leads to higher drive currents in the p-FETs. However, such surfaces are completely inappropriate for forming n-FET devices. The {100} silicon surfaces instead are optimal for forming n-FET devices due to the enhanced electron mobility along the {100} planes, which results in higher drive currents in the n-FETs.
Therefore, it is advantageous to form a semiconductor substrate having different surface orientations (i.e., hybrid surface orientations) that provide optimal performance for both the n-channel and p-channel complementary FET devices.
U.S. Patent Application Publication No. 2004/0256700 to Doris et al. describes a hybrid orientation substrate formed by wafer bonding, etching, and epitaxial regrowth. However, only one of the complementary device regions contained by such a hybrid orientation substrate has a buried insulator layer and constitutes a SOI structure, while the other of the complementary device regions does not contain any buried insulator layer and only constitutes a bulk structure.
Min Yang et. al. (M. Yang, et. al. Technical Digest of International Electron Devices Meeting, pp. 453, 2003) described a novel MOSFET structure for high performance CMOS using Hybrid Orientation Technology (HOT), where p-FETs were fabricated on a {110} surface orientation and n-FETs on a {100} orientation, by taking advantage of the carrier mobility dependence on surface orientation. However, in the HOT structures disclosed by Min Yang et al, one type of MOSFET is on SOI while the other one behaves bulk-like.
The benefits of SOT substrate structures over their bulk counterparts are well known, which include, but are limited to: reduction of junction leakage, reduction of junction capacitance, reduction of short channel effects, better device performance, higher packing density, and lower voltage requirements.
There is therefore a need to provide an improved hybrid orientation substrate having both complementary device regions configured as SOI structures for further improvements of the device performance.